1. Field of the Invention
The present invention relates generally to a an apparatus for testing integrated circuit carrier packages and more particularly, to a probe for testing the continuity of circuits within a printed wiring integrated circuit carrier package.
2. Description of the Prior Art
Until the advent of the side-brazed leadless packages, integrated circuit (IC) chips were mounted in dual-in-line package (DIP) devices having stamped or etched lead frames which included exterior contact pins integrally formed with each conductive lead member. Because of the integral conductor structure, it was therefore a rarity that any conductor of the DIP was not intact and thus the conductivity of each conductor was not normally questioned. However, since side-brazed leadless packages are manufactured in a substantially different manner than were prior art DIP devices, i.e., they are made by building up several layers of ceramic substrate having conductive strips electrochemically arrayed thereon with interconnections being made during processing, it has become necessary to test each lead of the device to insure conductivity between the exterior leg contact point and the interior contact points arrayed around the IC chip receiving cavity.
The standard prior testing approach has been to use individual probes to sequentially test each circuit within the package. However, as the interior contact points are only approximately 20 thousandths of an inch wide, a microscopic means to direct the test probe is required. It has proven to be difficult and time consuming to individually test each of the package conductors in this manner.
Another approach has been to use a testing plug which has individual circuits formed on the surface thereof. Each circuit is formed to make contact with a different interior contact point of the carrier package. To test the package a test current is passed through each plug circuit to each carrier circuit. The difficulty of this approach is that the individual circuits of the plug must be accurately aligned with the interior contact points in order to properly test the package. Alignment of the plug has proved to be difficult and time consuming. Also, as the interior contact points are usually not all disposed in exactly the same horizontal plane, it is difficult to achieve proper electrical contact.
A further approach has been to utilize a test plug composed of a conductive elastomer. The plug is inserted into the IC chip cavity in the carrier package so as to shunt each interior contact point to the other interior contact points. The package leads may be then tested for internal circuit continuity by testing the continuity between successive exterior contact points. This approach is inadequate and inefficient because the surface area of the contact between the elastomer and the IC contact points is very small and fails to provide uniform conductivity. Even moderate production requires a relatively uniform conductivity for automatic testing. Moreover, total process time of each device must be a very small fraction of a second. Conductive polymers are not suitable because they require from 1/4th of a second to one second to stabilize and establish conductivity through the material.